1. Field of the Invention
This invention relates to an electrically rewritable and non-volatile semiconductor memory device (EEPROM).
2. Description of Related Art
A write sequence of an EEPROM flash memory is usually performed by repeat of a write pulse application and the following write-verify for driving a data threshold distribution into a certain range. After the verify-read operation, verify-judgment (i.e., pass/fail detection) is performed for checking whether the entire write data have been written or not. In case the write completion is detected for all bits, the write sequence ends, while in case it is detected that there is an insufficiently written bit, the write voltage will be applied again.
The maximum, value of the number of write voltage applications, Nmax, (i.e., write cycle number or loop number) is usually predetermined. When data write completion is not detected in spite of that the write cycle number has already reached Nmax, the write sequence is finished in failure.
In a case that a flash memory system has an ECC function outside or inside of the chip, it will be permitted to contain certain failures (fail bit number or fail column number) determined with relation to the ECC function. Therefore, it is desirable that the fail number is detected at when the data write sequence ends in failure, and when the resultant is in a range of the permissible fail number, it is dealt with “pseudo-pass”.
From such the view point, there has already been provided a flash memory, in which the verify judgment can be performed at a high speed, and pass/fail can be detected with relation to the permissible fail number (refer to patent document 1: Unexamined Japanese Patent Application Publication No. 2002-140899).
In a flash memory with a large capacitance, it is usually used a redundancy system for relieving the memory of its defects. That is, there is prepared redundant cell arrays for so replacing a defect portion (for example a defective column) with a redundant cell array in such a case that permissible defects have been founded at a test time before shipment. Further, in the memory chip, there are prepared a defective address storage circuit and an address matching circuit for detecting address matching between the externally supplied address and the stored defective address in the defective address storage circuit. With these circuits, the defective address replacement may be controlled.
Usually, the defective address storage circuit is formed of a fuse circuit or a ROM circuit. Alternatively, there has been provided such a scheme that defective addresses are stored in the memory cell array together with various initial setup data without using the above-described fuse circuit and ROM circuit (for example, see patent document 2: Unexamined as Japanese Patent Application Publication No. 2001-176290).
In case the above-described redundancy system is adapted, it is in need of excluding the defective portion from the verify target in the verify-judgment. If not so, the data write cycle is repeated until the cycle number reaches the maximum value Nmax, and the write sequence ends in failure. This is the same as in the erase mode. Therefore, data latches are disposed in the verify-judgment circuit to store isolation data for isolating defective columns (see, the patent document 1).